Semiconductor Design Engineer

Organization & Role

The Teradyne Hardware Engineering team is looking for a highly-motivated, energetic, technically driven Semiconductor Engineer to focus on the development of ASIC and FPGA devices for products within the Semiconductor Test division. Development occurs in a dynamic and challenging multi-site development environment. This individual will report directly to the Integrated Circuit Engineering Hardware Engineering Manager.

We are looking for entry level, creative FPGA/ASIC Design and Verification Engineers to join our instrumentation development teams.

Employees are part of a team that delivers innovative and reliable solutions to meet the growing needs and complexity of our customers. The responsibilities of our  team members are focused on FPGA/ASIC design implementation, specification analysis and development, and design verification. Individuals will fill different roles over time, building from experience as a team contributor and ultimately acting as a team lead.  Employees will also experience and participate in the full product cycle as designs are taken from concept to shipping hardware.

Responsibilities

• Qualified applicants must be currently enrolled in BS or MS, EE or CE degree program with graduation date in the spring of 2021.
• Must be currently enrolled SR level in BS degree program with 3.2 GPA or greater, or
• Currently enrolled MS level students with minimum GPA of 3.2 or greater.
• Qualified applicants will have course work focused on FPGA/ASIC Design with Verilog or other HDL and course work focused on FPGA/ASIC Verification with Verilog or other HDL
• Must be available to work on site at the Tualatin, Oregon office as needed and when safe to do so. 
• Self-starter. Ability to recognize gaps in his or her own knowledge and seek out answers.

Basic Qualifications & Skills

Course work, projects or other experience opportunities with the following:

-Digital logic design

-Digital logic verification

-Microcontroller design

-FPGA/ASIC synthesis

-FPGA/ASIC PAR (Place-And-Route)

-High speed transmission line termination schemes

-Circuit timing with respect to bandwidth analysis, rise time, and fall time

Tool exposure desired:

-Linux and Windows operating systems

-All the common windows office tools (Excel, Word, Outlook)

-Verilog and/or SystemVerilog HDL languages

-UVM methodology

-Intel and/or Xilinx tool flows

-Csh, Python, Perl scripting languages

-C/C++ programming languages

Education

• Must be currently enrolled in BS or MS degree program with graduation date in the spring of 2021, studying EE or CE (Electrical Engineering) or (Computer Engineering)

#LI-ROMA