Analog Design Engineer (TERADYNE, Agoura Hills, CA)

Our Purpose  
TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day. 
 
We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results. 
 
Opportunity Overview 

Teradyne’s Semiconductor Test Division in Agoura Hills, CA is seeking a Analog Design Engineer to develop high-speed analog and mixed-signal ASICs for Automatic Test Equipment (ATE). The ideal candidate will have experience in CMOS circuit design and successful ASIC tape-outs, along with strong analytical, problem-solving, and communication skills. This role offers the opportunity to collaborate across multidisciplinary teams while leveraging AI-powered tools, automation, and data-driven methodologies to accelerate semiconductor innovation. A passion for emerging technologies, continuous learning, and technical excellence is highly valued.


Responsibilities include:

• Design and optimize high-speed analog and mixed-signal circuits from specification through transistor-level implementation.
• Validate and integrate designs using Cadence EDA tools across PVT corners, while supporting layout and ASIC integration.
• Participate in silicon characterization, debug, validation, and production test activities.
• Develop automation, scripting, and AI-assisted workflows to improve design productivity, verification, and data analysis.
• Collaborate across design, validation, test, and EDA teams to advance AI-enabled IC design methodologies.
  
  

All About You 
We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you’re ready to join us in this mission, take a closer look at the minimum criteria for the position. 

• MSEE or higher preferred, with 2+ years of experience in mixed-signal IC design and characterization; FinFET (16nm and below) experience is a plus.
• Strong knowledge of high-frequency analog/mixed-signal IC design, including PLLs, DLLs, ADCs, DACs, VCOs, CDRs, amplifiers, clocking circuits, high-speed I/Os, and CML designs.
• Solid understanding of CMOS device physics, semiconductor processes, PDKs, thermal effects, and electromagnetic principles.
• Experience throughout the IC development lifecycle, including silicon characterization and laboratory measurements.

• Familiarity with AI/ML techniques, generative AI, and large-scale data analysis for semiconductor design, validation, and test applications.

• Proficiency in scripting languages (Python/SKILL/Ocean) for automation and data analysis; Verilog/Verilog-A experience is a plus.

We are an equal-opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. 

Compensation: 
The base salary range for this role is $127,500 to $204,100. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.  

Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance.

Benefits: Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.  Please click here to see details. 

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