Analog Layout Engineer

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!

We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.

Our Purpose
TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day.

We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results.

Opportunity Overview
We are seeking a motivated and detail-oriented Junior ASIC Layout Design Engineer to join our semiconductor design team. The ideal candidate will assist in the physical design, layout, and verification of complex ASIC chips for advanced applications. This role provides an excellent opportunity for individuals passionate about hardware design and eager to grow their skills in an innovative and fast-paced environment.

• Assist in the creation of physical layout designs for ASIC circuits, including floor planning, placement, and routing using CAD tools.
• Collaborate with senior engineers on the development of block-level and top-level layout designs.
• Conduct layout verification, including DRC (Design Rule Checking), LVS (Layout vs. Schematic), and parasitic extraction to ensure design integrity.
• Work closely with the circuit design team to ensure optimal layout solutions for performance, area, and power requirements.
• Support the physical design team in timing closure, power optimization, and signal integrity analysis.
• Participate in tape-out processes and provide post-layout support for production.
• Maintain detailed documentation of design flows, methodologies, and results.

All About You
We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you’re ready to join us in this mission, take a closer look at the minimum criteria for the position.

• 7+ years of experience in analog layout design.
• Expertise in TSMC technology.
• Strong analog layout skills with expert-level proficiency in Cadence Virtuoso.
• Hands-on experience in the layout of analog blocks such as ADCs, DACs, and PLLs.
• Knowledge of high-speed analog circuit design.
• Ability to work independently on complex problems.
• Thorough understanding of layout considerations, including device matching, coupling, and noise isolation.
• Excellent verbal and written communication skills.
• Familiarity with semiconductor manufacturing processes and design rules.
• Strong analytical and problem-solving abilities.
• Attention to detail and high accuracy in layout design.
• Ability to work both independently and as part of a collaborative team.

Benefits:

Benefits: Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.  Please click here to see details.

#LI-NS1