Semiconductor Design Engineer

Organization & Role

Teradyne’s Silicon Technology Engineering (STE), Digital ASIC Group is responsible for developing advanced node ASICs for Teradyne next generation products such as SOC and Memory Test Instruments. Teradyne’s products in many ways must be ahead of the semiconductor industry in order for our customers to ship production chips/products.  You will join a best-in-class Digital team as a RTL Designer working in collaboration with an Analog team and product architects to develop Teradyne’s next generation large Mixed Signal ASICs. You will be involved in all phases of development including specification, architecture, design, verification, physical design, and silicon bring up.

Responsibilities

In this role you will be responsible for:

• Developing specifications, micro-architecture, and RTL design of mission critical blocks in collaboration with the chip architect
• Integration of industry standard and Teradyne custom Ips
• Collaborating with the verification team on test plans, debug support and coverage closure to ensure high quality RTL and first pass silicon success
• Providing timing constraints and STA support to the Physical Design team through timing closure
• Providing post silicon lab bring up and debug support

Basic Qualifications & Skills

• Extensive logic design experience writing RTL in Verilog
• Design of state machines, FIFOs, high speed data paths and arbitration logic and DFT
• Experience with logic synthesis and timing constraints
• Experience with clock domain crossings (CDC) and static timing analysis (STA)
• Experience with high speed memory interfaces, Serdes and PCIe preferred
• Experience with automation through scripting such as Perl, Python, Tcl & Make

Education

• BSEE or MSEE
• 10+ years of relevant industry experience

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