Mechanical Engineering Manager

Our Purpose
TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day.

We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results.

Opportunity Overview
The Memory Test Division is seeking a technically strong, highly motivated Engineering Manager to lead a team focused on interface development and signal delivery for high‑performance memory test platforms. This team is responsible for designing and optimizing the critical interconnects that enable clean, reliable, high‑speed signaling to advanced memory devices. 

This position is based in San Jose, CA, operating within a fast‑paced, multi‑site engineering environment. You will report to the director and collaborate closely with teams across signal integrity, hardware design, mechanical engineering, and system architecture. 

• Direct engineering activities related to memory‑test interface hardware, including load boards, probe interfaces, connectors, cabling systems, and other signal delivery. 

• Manage department budgets, staffing, personnel development, and recruitment for the interface team. 

• Lead a multidisciplinary team specializing in signal integrity, interconnect design and validation, materials, and electromechanical integration 

• Build and execute a roadmap for interface improvements aligned with memory‑test performance, reliability, and manufacturability targets 

• Establish KPIs for signal quality, interface reliability, and test‑system performance; report progress to senior leadership 

• Collaborate with suppliers and external engineering partners to develop signal delivery solutions and interconnect. 

• Promote a culture of engineering rigor, signal‑integrity awareness, and continuous improvement across the Memory Test Division 

All About You
You thrive in complex technical environments and are motivated by solving high‑speed signaling and interface‑architecture challenges. You enjoy leading teams, shaping technical direction, and building robust hardware that supports next‑generation memory devices. 

• Bachelor’s degree in Electrical Engineering, Mechanical Engineering, or related field 

• 8+ years of experience in electrical, mechanical, or electromechanical design within semiconductor equipment or high‑speed hardware systems 

• Demonstrated expertise in signal delivery, interconnect design, high‑speed routing, or interface hardware development 

• Strong background in design optimization, materials evaluation, and process improvements 

• Proven ability to manage external design partners or contract engineering resources 

• Excellent communication skills—oral, written, and presentation 

• Broad technical fluency across hardware, software, mechanical, thermal, and system‑level domains 

• Deep understanding of the development lifecycle for electro‑mechanical products 

• Some travel overseas may be required – expect once per year. 

We are only considering candidates local to position location and are unable to provide relocation for this position.

This position is not eligible for visa sponsorship.

Compensation:
The base salary range for this role is $160,00 – 256,100. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance. 

Benefits:

Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.  Please click here to see details. 

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