Signal Integrity Engineer

Organization & Role

Signal Delivery Architect

The Nextest Business Unit of Teradyne is looking for a highly-motivated, energetic, technically driven engineer to focus on the development of hardware for memory test systems. Development occurs in a dynamic and challenging multi-site development environment. 

Responsibilities

You will play a critical role as the signal delivery architect for the Nextest business unit.  As a Signal Integrity Architect you will be responsible for signal delivery problems across all memory products at Teradyne.  This includes ASIC to board signaling, ASIC to ASIC in a board, and off board signaling through connectors and coaxial cables.  The position will require good working knowledge of common simulation tools as well as the development of physical test fixtures to verify design.  They will also be expected to help with design review of critical PCBs for signal integrity concerns.  Good communications skills and ability to work with physically dispersed teams is a strong requirement.  A key ability is being able to take common simulation outputs such as S-parameters from various components and understand at the system level will the product meet customer performance requirements.

Basic Qualifications & Skills

The successful candidate will have 15+ years experience with High Speed Signal Delivery Design and Evaluation.  This includes both signal integrity within a PCB and off the board (board to board connectors, ribbon cables, coaxial cable, etc.). 

• PCB design fundamentals (single ended and differential signals)
• Signal loss
• Impedance control
• Crosstalk (near end and far end)
• Familiar with single-ended and differential signaling up to 50Gbps
• Familiar working with component models (touchstone files) and cascading models to generate complete system models for simulation
• Simulation of digital interfaces (examples would be FPGA to DRAM, SERDES interfaces)
• Simulation of analog paths through a combination of PCB, connector, and cable (examples would be signal driver to DUT)
• Very familiar with 2D and 3D simulation tools (examples include ADS, ANSYS HFSS, Sigrity)
• Electrical length calculations for signal matching
• Familiar with looking at signals in both frequency (S-parameter) and time domain and understand how to interpret results when it comes to suitability for a particular application. 
• Familiar with generating and interpreting data-eye diagrams up to 50Gbps: NRZ, PAM3, PAM4, PAMx
• Familiar with Allegro or similar layout tool and schematics:
• PCB Stackup design and familiar with fabrication limitations and cost trade-offs
• High Frequency board material experience
• Significant experience with measuring signal performance in the lab: TDR measurements and VNA measurements
• Able to develop test fixtures for making measurements (both custom design test boards as well as making “ad hoc” probing solutions to troubleshoot existing PCBs)
• Familiar with the cost vs performance tradeoffs when designing signal paths as cost is key design constraint
• Experience with flex circuit design for high speed signaling

Location

                San Jose, CA or Agoura Hills, CA

Education

BSEE, MSEE, PhD or equivalent experience

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