Digital Verification Engineer
Alajuela, CR
We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!
Duties & Responsibilities
Digital functional verification engineer responsible for the planning, strategy, and execution of challenging FPGA verification projects. Work under the technical supervision of a Verification Lead. The position requires interfacing with other functional groups (e.g. PCB, software, applications).
Required skills/experience:
- Experience with verification planning tool to create verification plans or testplans (e.g. Cadence ePlanner)
- Experience with System Verilog and at least one functional verification methodology: UVM (preferred), OVM, or VMM
- Experience with advanced verification techniques: constrained random, feature driven verification, transaction level verification.
- Experience with at least one assertion language: SVA, PSL or OVL
- Expertise in testbench architecture, testbench development and Verification IP integration
- Experience with Scoreboards, reference models development and integration (e.g. SystemC, C/C++, Matlab...)
- Experience writing automation scripts (e.g. Makefiles, shell programming, TCL, Perl, Python)
- Experience working with revision source control (e.g. clearcase, git, svn)
- Good English language communication and documentation skills.
- Detailed oriented with the ability to bring issues to closure.
Education
- Bachelor’s Degree or equivalent in Electrical Engineering/Computer Engineering/Computer Science or closely related field with a minimum of 5 years of relevant work experience
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