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Sr Digital Verification Lead

ID:  4886
Function:  Engineering

Alajuela, CR

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!

Organization & Role

Act as a digital functional verification technical lead responsible for the planning, strategy, and execution of challenging FPGA verification projects. Provide technical leadership for large, cross-site verification teams. The position requires interfacing with other functional groups (e.g. PCB, software, applications).


Required skills/experience

  • Experience with verification planning tool to create verification plans or testplans (e.g. Cadence ePlanner) 
  • Proficient with System Verilog and at least one functional verification methodology: UVM (preferred), OVM, or VM)
  • Proficient with at least one assertion language: SVA, PSL or OVL
  • Expertise in testbench architecture, testbench development and Verification IP integration
  • Experience with Scoreboards, reference models development and integration (e.g. SystemC, C/C++, Matlab...)
  • Knowledge of at least one of the following protocols/technologies: Ethernet, PCIe, USB, AXI, AHB, I2C, SPI, I2S, MIPI, DRAM, FLASH
  • Experience with regression failures analysis
  • Experience with verification tracking metrics
  • Experience writing automation scripts (e.g. Makefiles, shell programming, TCL, Perl, Python)
  • Experience leading verification teams


  • Master’s Degree or equivalent in Electrical Engineering/Computer Engineering/Computer Science or closely related field with a minimum of 6 years of relevant work experience

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