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Logic Design Engineer - New College Graduate

ID:  5187
Function:  Engineering

North Reading, MA, US

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!

Organization & Role


The responsibilities for a Logic Design Engineer would be to specify, design, verify and validate field programmable gate arrays (FPGA) and/or application specific integrated circuits (ASIC) that are used in Automated Test Equipment.   



  • Deriving requirements from higher level specifications
  • Writing design documents
  • Designing and implementing register-transfer-level (RTL) code using Verilog
  • Designing with Vendor IPs and various industry standard interface protocols
  • Use of digital simulation tools to verify designs
  • Creation of physical design constraints for placement, timing closure and CDC
  • Implementation of designs into target technologies using synthesis and place and route tools
  • Perform timing analysis using static timing analysis tools
  • Perform lab debug of designs with laboratory equipment such as Logic Analyzers and oscilloscopes
  • Collaboration with other logic designers, board designers, software designers and ASIC designers
  • Communicating status to project leadership

Basic Qualifications & Skills


  • BS in EE with GPA of 3.0 or better
  • Knowledgeable in digital logic design
  • Experience in logic design writing RTL in the Verilog HDL
  • Familiarity with a scripting language such as Python, TCL and Perl
  • Experience with logic synthesis
  • Good oral and written skills
  • Good ability to work in a team environment


Desired Qualifications & Skills


  • Familiarity with either Xilinx(AMD) or Altera(Intel) FPGAs and tools
  • Familiarity with high-speed serial protocols including PCIe and Ethernet.
  • Familiarity with a digital simulation tool such as Synopsys VCS, Cadence NCSIM(preferred) or Mentor QuestaSim
  • Familiarity with C/C++
  • Familiarity in the use of a source control tools
  • Familiarity working in a Linux based development environment




BS in EE with GPA of 3.0 or better

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