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ASIC Design Engineer

ID:  2282
Function:  Engineering
Location: 

North Reading, MA, US


We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!.

Organization & Role

 

The Teradyne Hardware Engineering team is looking for a highly-motivated, energetic, technically driven Semiconductor Engineer to focus on the development of ASIC and FPGA devices for products within the division. Development occurs in a dynamic and challenging multi-site development environment. This individual will report directly to the Hardware Engineering Manager.

Responsibilities

 

Teradyne’s Silicon Technology Engineering (STE), ASIC Integration Group is responsible for developing advanced node ASICs for Teradyne next generation products such as SOC and Memory Test Instruments. Teradyne’s products in many ways must be ahead of the semiconductor industry in order for our customers to ship production chips/products.

You will join a best-in-class Digital team as an ASIC Design Engineer developing Teradyne’s next generation large Mixed Signal ASICs. You will be involved in all phases of a netlist hand-off flow including synthesis, CDC, LEC and STA.

 

In this role you will be responsible for:

  • Perform RTL to Netlist tasks such as synthesis, LEC, CDC
  • Develop and maintain the tool flow to support the project
  • Work with Team to enhance PD methodology

Basic Qualifications & Skills

 

  • Mid Level experience in ASIC development 
  • Experience in advanced node processes 16nm and below
  • Experience with industry standard tools, preference for Cadence flow
  • Basic understanding of RTL to GDSII flow
  • Basic understanding of timing constraints and static timing analysis (STA)
  • Experience with Synthesis
  • Experience with CDC (Clock Domain Crossing Checks) preferred
  • Experience with LEC (Logic Equivalence Checks) preferred
  • Experience with automation through scripting such as Perl, Python, Tcl & Make

 

Education

 

BSEE or MSEE

 

This job requires the individual to be fully vaccinated against COVID-19 prior to the first day of work or receive a reasonable accommodation from the vaccine requirement based on a valid medical or religious exemption. 

 

We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.


Nearest Major Market: Boston

Job Segment: Manufacturing Engineer, Engineer, Design Engineer, Electrical Engineering, Hardware Engineer, Engineering