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FPGA Design Engineer

ID:  4894
Function:  Engineering
Location: 

San Jose, CA, US Tualatin, OR, US


We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!

Organization & Role

 

Nextest is a global technology company of Teradyne delivering progressive solutions to complex testing challenges. Without creativity and the diversity of thought, Nextest technological innovations would not leave the ground. If you are excited at the prospect of joining a global team, that is both exciting and dynamic, then Teradyne may be the place for you!

We develop test instrumentation for some of the world’s most advanced and highest performance integrated circuits.  Our products integrate state-of-the-art digital and analog designs using leading edge ASIC and FPGA technologies, liquid cooling, and high density / high performance signal delivery.
 
We are a small, close-knit team working in an exciting, focused atmosphere.  We are looking for an experienced FPGA Design Engineer with outstanding technical skills and leadership potential. The candidate should have a strong desire to contribute to a team-oriented project where what matters most is our success in bringing products to market quickly with exceptional quality and reliability.

Responsibilities

 

•    Architect and implement FPGA solutions to support next generation Flash and DRAM test instrumentation.
•    Turn abstract concepts and customer requirements into reliable, extensible, and supportable designs. 
•    Assist in the maintenance and extension of existing FPGA designs to support quality improvement and emerging customer requirements.
•    Maintain schedule commitments and deliver high quality end products.
•    Occasional travel may be required.

Basic Qualifications & Skills


•    Experience with Digital Design and Architecture
•    RTL coding, synthesis, timing closure and lab validation
•    Experience with Static Timing Analysis of ASICs or FPGAs
•    Experience with digital simulation testbench creation
•    Experience with C or C++
•    Familiarity with lab equipment such as oscilloscopes, power supplies and waveform generators. 

 

Additional Desired Skills


•    FPGA Transceiver based design experience
•    Experience with DRAM and Flash Memory interfaces
•    Experience with Intel/Xilinx FPGA tool flows
•    Proficiency with Verilog HDL Language
•    Familiarity with UVM Methodology
•    Scripting languages experience 
•    Linux and Windows operating systems experience
•    Familiarity with ATE instrumentation
 

 

Education

•    Master’s Degree or equivalent in Electrical Engineering or closely related field with a minimum of 3 years of relevant work experience
OR
•    Bachelor’s Degree or equivalent in Electrical Engineering or closely related field with a minimum of 5 years of relevant work experience

 

 

 

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Nearest Major Market: San Jose
Nearest Secondary Market: Palo Alto

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