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Sr. Verification Lead

ID:  3862
Function:  Engineering

San Jose, CA, US North Reading, MA, US Tualatin, OR, US

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!

Organization & Role

Nextest is a global technology company of Teradyne delivering progressive solutions to complex testing challenges. Without creativity and the diversity of thought, Nextest's technological innovations would not leave the ground. If you are excited at the prospect of joining a global team, that is both exciting and dynamic, then Teradyne may be the place for you!

We develop test instrumentation for some of the world’s most advanced and highest performance integrated circuits.  Our products integrate state-of-the-art digital and analog designs using leading edge ASIC and FPGA technologies, liquid cooling, and high density / high performance signal delivery.

We are a small, close-knit team working in an exciting, focused atmosphere.  This role requires a Senior Digital Verification Technical Lead with at least 12 years of experience, outstanding technical skills and leadership potential. The candidate should have a strong desire to contribute to a team-oriented project where what matters most is our success in bringing products to market quickly with exceptional quality and reliability.


Responsible for the planning, strategy, and execution of challenging FPGA verification projects. Provides technical leadership for large, cross-site verification teams. The position requires interfacing with other functional groups (e.g. software, applications). 

Basic Qualifications & Skills

Experience with verification planning tool to create verification plans or testplans (e.g. Cadence ePlanner)  
•    Proficient with System Verilog and at least one functional verification methodology: UVM (preferred), OVM, or VMM
•    Proficient with advanced verification techniques: constrained random, feature driven verification, transaction level verification.
•    Proficient with at least one assertion language: SVA, PSL or OVL
•    Expertise in testbench architecture, testbench development and Verification IP integration
•    Experience with Scoreboards, reference models development and integration (e.g. SystemC, C/C++, Matlab...)
•    Knowledge of at least one of the following protocols/technologies: Ethernet, PCIe, USB, AXI, AHB, I2C, SPI, I2S, MIPI, DRAM, FLASH
•    Experience with regression failures analysis
•    Experience with verification tracking metrics
•    Experience writing automation scripts (e.g. Makefiles, shell programming, TCL, Perl, Python)
•    Experience working with revision source control (e.g. clearcase, git, svn)
•    Good English language communication and documentation skills.
•    Successful completion of at least 10 verification projects
•    Ability to track and bring issues to closure. Detailed oriented. Excellent planning and organizational skills. 
•    Experience leading large, multi-site verification teams: planning, managing, and tracking verification team for on-time delivery
•    Experience mentoring junior engineers


Desired skills / experience:
•    Experience in verification of Automated Test Equipment functionality 
•    Static and/or dynamic Formal Verification
•    Experience with GVP source control continuous integration tool



•    BS or MS in Electrical Engineering, Computer Engineering or Computer Science


Nearest Major Market: San Jose
Nearest Secondary Market: Palo Alto

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